So these people have been out here since earlier this year with this idea, and I think they raised a bit of money. There are a few problems that make me immediately hesitant to believe this is useful at all though:
they have been incredibly vague about they intend this to work
they’ve said they’ve shipped this around already, and are still looking for a partner to test with
whatever the solution actually, it’s not a drop in
it would not only require a custom compiler, but a rewrite of any existing software
it’s process-oriented and can’t be patented (at least in the states), so any chip maker could just take the idea and do their own implementation
Best possible case is that it works, and their compiler and tooling can help with simplified refactoring of code, making that part the actual product that makes them a useful company.
Worst case is it’s a total BS idea. Hesitant to say anything like that until we hear what the downsides are from a tested proof of concept
Whatever the outcome, it just isn’t that big of a draw when you’re thinking about very specific workloads that can function in this type of parallelism. As they’ve already mentioned, they’ve mocked this on an FPGA, so why wouldn’t devs just build and run this specific work on something like AMD’s FPGA chips in a DC setting and get even 75% of the way there?
I feel like anything they think they’ve come up with isn’t as beneficial as they are presenting. Not that no one else can innovate, but I really think if it was so simple or feasible, one of the big chip makers would have already done it.
Very specific things could be, but I don’t think there’s a real need to build an entire company on it unless you’re desperate to get bought for an idea.
I don’t see them having a second and third idea to really keep an entire company going, and at that point, just work out how to build your own thing.
So these people have been out here since earlier this year with this idea, and I think they raised a bit of money. There are a few problems that make me immediately hesitant to believe this is useful at all though:
Best possible case is that it works, and their compiler and tooling can help with simplified refactoring of code, making that part the actual product that makes them a useful company.
Worst case is it’s a total BS idea. Hesitant to say anything like that until we hear what the downsides are from a tested proof of concept
Whatever the outcome, it just isn’t that big of a draw when you’re thinking about very specific workloads that can function in this type of parallelism. As they’ve already mentioned, they’ve mocked this on an FPGA, so why wouldn’t devs just build and run this specific work on something like AMD’s FPGA chips in a DC setting and get even 75% of the way there?
I feel like anything they think they’ve come up with isn’t as beneficial as they are presenting. Not that no one else can innovate, but I really think if it was so simple or feasible, one of the big chip makers would have already done it.
Very specific things could be, but I don’t think there’s a real need to build an entire company on it unless you’re desperate to get bought for an idea.
I don’t see them having a second and third idea to really keep an entire company going, and at that point, just work out how to build your own thing.
Yeah that’s a solid point. Make out with the venture capital for a bit and then get bought by a bigger fish